Article : Using Self-Immunity Technique 64-bit Register File Immunity Improvement

Title

Using Self-Immunity Technique 64-bit Register File Immunity Improvement

Author

Ravi Krishna Penukuduru, S M L V Durga

The vulnerability of microprocessors against soft errors even in terrestrial Applications increases due to Continuous shrinking in feature size, increasing power density etc. The essential Architectural component where soft errors can occur in regular manner is register file. These errors may rapidly spread from there throughout the whole system and the output results my get damage. Thus, when it comes to reliability register files are recognized as one of the major concerns. This paper introduces Self-Immunity, a technique that improves the integrity of the register file with respect to soft errors. Based on some surveys and observations it is concluded that a certain number of register bits are not always used to represent a value stored in a register. This paper deals with the difficulty to exploit this obvious observation to enhance the register file integrity against soft errors. We show that we can reduce the vulnerability of the register file considerably while exhibiting smaller overhead in terms of area and power consumption compared to state-of-the-art in register file protection by our technique. Here we go for a 64-bits register.

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