Fast Fourier Transform (FFT), which serves as an efficient and ubiquitous tool for computing Discrete Fourier Transform (DFT), is popular for transforming a signal from time domain to frequency domain. Since FFT algorithm requires less number of computations than direct evaluation of DFT, this technique has been widely used in speech recognition (massively used now days in many application lines and products), telecommunication, signal processing, multimedia communication, etc. Designing and implementing the floating-point (FP) FFT Algorithms in FPGA is always the hot research spot and is still a challenging task. This paper proposes a new architecture of an FFT core that computes radix-2 8-point FFT using fixed-point operation in only eight clock cycles. The key feature of this design is that it tries to maintain better performance with minimal possible footprint. The design is done in Xilinx ISE 13.2 tool using Verilog-HDL. The processor core has been simulated using Xilinx ISIM simulator for the functional verification and its FPGA based implementation has been successfully verified using Spartan-3E Starter Kit. This paper also aggregates a brief analysis of the performance of FFT Core and the consumption of FPGA resources by the designed core. The objective of this work is to get an area and time efficient architecture that could be used as a part of a voice processing system.
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