Article : Memory Efficient Distributed Architecture LUT Design Using Unified Architecture

Title

Memory Efficient Distributed Architecture LUT Design Using Unified Architecture

Author

S.M.L.V.K. Durga, N.S. Govind

In this paper, an efficient algorithm for optimizing the size of a LUT required for the direct storage of complex computational values and a FIR System based on optimized LUT is implemented. So far, many algorithms have been implemented for optimizing Look-up-tables (substitute the multiply and accumulate structures contained in FPGAs) of DSP cores in FPGAs. In this paper, a new method “A-OMS LUT” is presented to provide better performance than the previously specified methods [3, 5, 6]. In addition, a simple FIR filter is implemented through an A-OMS algorithm using Look Up Tables (LUT) for high-speed computations in FPGAs and is applicable for Communication Technologies i.e. wireless technology especially for spectrum sensing techniques in cognitive radio of a Software Defined Radio and like-wise. Further, the memory optimization process based on A-OMS LUT algorithm is shown, which further enhances the system performance in terms of speed and area that doubles the transmission rate, increasing the overall throughput. Finally, the experimental results show more than 30% of saving in area-delay product with a transmission speed of twice that of the conventional methods. Xilinx synthesis tools are used to implement the entire design process and is simulated using Xilinx ISE 7.1 Project Navigator.

Sign-in to continue reading Full Article
 
 

 

Pay only for this article and continue reading the full article

Price

Indian Member   40.00

Others Member   3.00

 

 

 

Content

Submit Article

iJARS Group invites Genuine Research Papers on Modern/Advanced trends in various fields of study.

To submit an article

Click Here

Content

Conferences

Associate your Conference with us Click here

Suggest a New Conference Click here

Upcoming Conferences Click here