The important aspect of VLSI design is its power reduction technique through its design. The Dynamic power loss in Finite Impulse Response filter (FIR) is reduced by the architecture we propose in this paper. We propose a dynamically adaptive filter architecture which improves filter performance and reduces the power consumption. The power consumption is reduced by reducing the dynamic power loss in the filter. The FIR filter operates with input amplitudes and the coefficients. The input amplitudes have large variations in the data due to which Filter operation becomes complex and the power consumption too increases. The FIR filter dynamically adapts to filter order based on the input amplitudes and the coefficients. This architecture exhibits an improved performance and reduced power consumption with efficient trade off for Area. The delay is reduced by the multipliers used in the filters. The modified Booth multipliers are used to improve the performance. The modified booth multiplier consumes less power and operates faster compared to normal multipliers. Analysis on performance, power and area proves that this design suits well for both dynamically changing and fixed order filters. Experimental results shows improved filter performance and significant power savings is achieved with minor area degradation. Without seriously compromising with filter area, the proposed approach reduces delay and power compared to the conventional method.
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