The never ending need for low-power and low-noise digital circuits has intrigued designers to explore new options in the world of circuit design. One approach that seems to be very promising is the famous energy-recovering (adiabatic) logic. Adiabatic circuits pursue low energy dissipation by restricting the current to flow across devices with low voltage drop and by recycling the energy stored in the capacitors. The energy consumption is analyzed by variation of parameters. In the analysis, two logic families, ECRL (Efficient Charge Recovery Logic) and PFAL (Positive Feedback Adiabatic Logic) are compared with conventional CMOS logic for inverter and 2:1 multiplexer circuit and Ring counter. The results show that adiabatic technique is a good choice for low power and low area application in specified frequency range.
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